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1 ? integrated xscale regulator the isl6271 is a versatile power management ic (pmic) designed for the xscale type of processors . the device integrates three regulators, two fault indicators and an i 2 c bus for communication with a host microprocessor. two of the three regulators function as low power, low drop out regulators, designed to power sram and phase-lock loop circuitry internal to the xscale processor. the third regulator uses a proprietary switch-mode topology to power the processor core and facilitate dynamic voltage management (dvm), as defined by intel. since power dissipation inside a microprocessor is proportional to the square of the core voltage, intel xscale processors implement dvm as a means to more efficiently utilize battery capacity. to support this power saving architecture, the isl6271 integrates an i 2 c bus for communication with the host processor. the processor, acting as the bus master, transmits a ?voltage level? and ?voltage slew rate? to the isl6271 appropriate to the processing requirements; higher core voltages support higher operating frequencies and code execution. the bus is fully compliant with the phillips? i 2 c protocol and supports both standard and fast data transmission modes. alternatively, the output of the core regulator can be programmed in 50mv increments from 0.85v to 1.6v using the input voltage id (vid) pins. all three regulators share a common enable pin and are protected against overcurrent, over temperature and unde rvoltage conditions. when disabled via the enable pin, the isl6271 enters a low power state that can be used to conserve battery life while maintaining the last programmed vid code and slew rate. an integrated soft-start circuit transitions the isl6271 output voltages to their default values at a rate determined by an external soft-start capacitor. pinout isl6721 (4x4 qfn) top view features ? three voltage regulators (1 buck, 2 ldos) ? high-efficiency, fully-integrated synchronous buck regulator with dvm ? proprietary ?synthetic ripple? control topology ? greater than 1mhz switching frequency ? diode emulation for light load efficiency ?i 2 c interface module for dvm from 0.85v to 1.6v ? optional fixed 4-bit vid-control in lieu of dvm ? small output inductor and capacitor ? battery fault signal ? input supply voltag e range: 2.76v?5.5v ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile applications ?pda ? cell phone ? tablet devices ? embedded processors related literature ? technical brief tb379 ? thermal characterization of packaged semiconductor devices? ? technical brief tb389 ? pcb land pattern design and surface mount guidelines for qfn packages? soft bflt# bbat en gnd vid3 phase pvcc pgnd pgood vcc scl/vid0 sda/vid1 viden vid2 lvcc vsram fb vpll vout 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 ordering information part number temp. range (c) package pkg. dwg. # isl6271cr -25 to 85 20 ld 4x4 qfn l20.4x4 ISL6271CR-T 20 ld 4x4 qfn tape and reel fn9058 preliminary isl6271 data sheet july 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004. all rights reserved intel? is a registered trademark of intel corporation.. all other trademarks mentioned are the property of their respective own ers.
2 regulator block diagram functional block diagram ldo1 ldo2 switching regulator dac i 2 c & static vid logic viden vid2 vid3 sda (vid 1) scl (vid 0) pvcc en lvcc figure 1. bulverde power controller vsram (vcc_sram) vpll (vcc_pll) vout (vcc_vcore) lo c ss gate drive & zero current detect + - vout + - error amp + - pvcc phase pgnd ripple amp por temp monitor vout gnd vout fb soft ov uv cmp 2.6v to 5.5v gate drive logic c c r c r comp c rp r rp dac uv ot pgood vcc viden scl/vid0 sda/vid1 vid2 vid3 bbat bflt# en ov ldo1 and ldo2 1.3v vpll 1.1v vsram lvcc 1.8v to 5.5v 50 ? ring damping circuit c in cout figure 2. functional block diagram overcurrent detect i 2 c vcc_core monitor isl6271
3 absolute maximum rati ngs thermal information supply voltage (pvcc, vcc, lvcc). . . . . . . . . . . . . . . . . . . . . . .7v signal input voltage (en, vid (note 1), viden) . . . . gnd-0.3 to 7v esd rating human body model (per mil-std-883 method 3015.7) . . . . .3kv machine model (per eiaj ed-4701 method c-111) . . . . . . . .200v operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . .-25c to 85c supply voltage (pvcc, vcc) . . . . . . . . . . . . . . . . . . . . 2.76 to 5.5v supply voltage (lvcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 - 5.5v thermal resistance ja (c/w) jc (c/w) 4x4 qfn package (notes 2, 3) . . . . 45 7.5 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. switching frequency is a function of input, output voltage and load. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures (tb379). 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions, unless otherwise noted; t a = -25c to 85c, pvcc, vcc = 3.7v. component values as shown in figure 19, typical appl ication circuit: vout = 1.6v. parameter symbol test conditions min typ max units core buck regulator output voltage nominal range vout programmable in 50mv increments 0.85 1.60 v max. dc output current icore 600 ma current limit (dc plus ripple) icore_lim (wafer level test only) 700 800 ma pmos on resistance r ds(on)p iout = 200ma 275 m ? nmos on resistance r ds(on)n iout = 200ma 140 m ? frequency (note 4) f vin = 3.7v, vo = 1.0v 1.2 mhz load regulation vout = 1.6v; io = 1ma?500ma 0.05 1 % line regulation over vcc range 1 % pk-pk ripple v p-p vout = 1.6v, i = 0.4a, ccm 5 mv discontinous mode operation 10 mv system accuracy over temperature -1 2 % room temperature -1 1 % undervoltage threshold (note 5) rising, as % of nominal vout 94 % falling, as % of nominal vout 86 % overvoltage threshold rising, as % of nominal vout 114 % falling, as % of nominal vout 106 % start-up time t st from enable active @ io = 10ma; vo = 1.6v 1.3 ms ring damping switch resistance r on(rd) 50 75 ? linear regulators input voltage lvcc connected to pvcc 1.70 5.5 v not connected to pvcc 1.70 3.5 v output voltage vsram 1.1 v vpll 1.3 v output tolerance iout = 1ma -2.5 2.5 % isl6271
4 maximum average output current i_sram 50 ma i_pll 30 ma current limit i ldo_lim each ldo regulator 120 300 % (note 7) line regulation lvcc = 1.7?5.5v 0.25 % load regulation io = 1 to 25ma 0.5 % undervoltage threshold rising - % of vpll, vsram 91 % falling - % of vpll, vsram 86 % start-up time tst soft-start power up to 1.3v, csoft = 10nf 1.3 ms system supply current (vcc) i q i core = no load 380 a i q en = 0v 2 5 a supply current (lvcc) i lvcc 25 a en voltage v ih 2.0 v v il 0.55 v soft-start source current (controlled by i2c control bits d5, d4) i 00 2.75 4.8 7.25 a i 01 5.4 9.4 14.5 a i 10 13.5 23.4 36 a i 11 27 46 72 a temperature shutdown t r rising t 130 140 150 c t f falling t 85 95 105 c por/bflt# threshold (note 6) v por rising vcc 2.60 2.80 3.0 v v por falling vcc 2.44 2.60 2.76 v pgood pull down resistance r on 700 960 ? viden, vid2, vid3 voltage threshold v ih(vid) 2.4 v v il(vid) 1.0 v i 2 c logic scl, sda voltage threshold v ih(i 2 c) 2.0 v v il(i 2 c) 0.55 v sda pull down resistance r on(sda) 132 ? notes: 4. switching frequency is a function of input, output voltage and load. 5. as a result of an overcurrent condition exc eeding 600ma. will result in a pgood fault. 6. a high rising por tracks with a high falling por. 7. percentage of maximum average output current (i_sram or i_pll). electrical specifications operating conditions, unless otherwise noted; t a = -25c to 85c, pvcc, vcc = 3.7v. component values as shown in figure 19, typical appl ication circuit: vout = 1.6v. (continued) parameter symbol test conditions min typ max units isl6271
5 typical operating performance test results from the intersil isl6271 customer reference board (crb). output filter on switcher made up of a 3.3h drumcore wi th 100m ? of dcr and an output capacitance of 4.7f. x5r; rcomp = 100k ? , vin = 3.7v unless otherwise noted. figure 3. switching frequency regulation figure 4. vsram line-load regulation fi gure 5. switching regulator efficiency 50ma to 260ma load step on vout. top: output voltage, 50mv/div; phase node, 5v/div.; inductor current, 200ma/div, 2s/div figure 6. dcm to ccm top: phase node output voltage ripple, 10mv/div. bottom: inductor current, 100ma/div, 1s/div figure 7. ccm to ccm 00.1 70 72 74 76 78 80 82 84 86 88 90 load current efficiency 0.2 0.3 0.4 vin = 3.6, vout = 0.85 vin = 3.0, vout = 0.85 vin = 3.6, vout = 1.4 vin = 3.0, vout = 1.4 1.085 1.086 1.087 1.088 1.089 1.09 1.091 1.092 1.093 1.094 1.7 2.5 3.5 input voltage output voltage iout = 85ma io = 10ma io = 25ma iout = 55ma 1.301 1.302 1.303 1.304 1.305 1.306 1.307 1.308 1.309 1.7 2.5 3.5 input voltage output voltage iout = 65ma io = 5ma io = 20ma iout = 55ma vout iout phase isl6271
6 i 2 c vout = 0.85 to 1.6v 5mv/s, 40s/div figure 8. typical i 2 c communication top: phase node output voltage ripple, 10mv/div bottom: inductor current, 100ma/div, 1s/div figure 9. ripple in dcm ripple in dcm: fripple = 145khz, vin = 2.85v, vout = 0.85v, iout = 10ma ripple = 10mv (worst case), 1s/div figure 10. phase node to dcm ldo transient response with 3.3f output capacitance. lvcc = 4.1v. 10ma dc load+ 55ma step load. figure 11. ldo transient response ripple in ccm vin = 2.85v, vo = 0.850v, fripple = 1mhz, io = 500ma, ripple = 4.2mv, 400ns/div figure 12. ripple in ccm soft-start into ccm, vin = 4.2v, ch3 = en pin. vout = 0.85 soft-start capacitor = 10nf. 200s/div figure 13. soft-start into ccm typical operating performance (continued) test results from the intersil isl6271 customer reference board (crb). output filter on switcher made up of a 3.3h drumcore wi th 100m ? of dcr and an output capacitance of 4.7f. x5r; rcomp = 100k ? , vin = 3.7v unless otherwise noted. data clk vout load step trigger vsram, 20mv/div output voltage ripple soft pin vout en pin isl6271
7 functional pin description pvcc - input power to the core s witching regulator. this voltage is typically supplied by a the primary, single-cell li-ion battery or power adapter. vcc - voltage source for control circuitry. must be held within 0.2v of pvcc. bbat - secondary back-up voltage used to provide an indication of the main battery status when the main battery is low or absent. bbat is typically a coin cell device and must be maintained between 1.5v and 3.75v. phase - the output switching node that connects to the output inductor to generate the processor core voltage. vout - output voltage of the core regulator. programmable from 0.85 to 1.6v via the integrated i 2 c bus or vid pins. lvcc - input voltage to the vsram and vpll ldo pass elements. to minimize power loss across the pass element this should be tied to a pre-regulated system voltage between 1.8v and 2.5v. lvcc can operate from the main battery input when lower voltages are unavailable. vpll - 1.3v ldo regulator designed to supply power to the phase-locked loop circuitry internal to the microprocessor. vsram - 1.1v ldo regulator designed to supply power to the microprocessor sram circuitry. fb - core voltage feedback (to the error amplifier) via an external compensation resistor. soft - an external capacitor connected between this pin and ground controls the regulators output rise time. the start-up ramp begins when vcc reaches its power-on-reset (por) rising threshold and the en pin is high. en - the isl6271 outputs are enabled when a voltage greater than 2v is applied to the en pin. the core regulator output mosfets bridge is turned off and the ldos are disabled when en is pulled low. bflt# - battery fault indicator. a high level indicates the adequacy of the battery for regulator start-up. designed to interface with the processor gene ral purpose io, this pin is actively pulled low when the main battery is absent. pgood - an open-drain output that indicates the status of the three regulators. it is pulle d low when any of the regulators are outside their voltage tolerances. viden - pull this pin low to enable i 2 c communication. connecting this pin to vcc disables the i 2 c bus and enables the vid inputs. in this mode the slew rate is fixed at a value determined by the soft-start capacitor. scl (vid0) - this is a dual function pin. when viden is low it acts as the i 2 c clock input (scl). when viden is high this pin acts as bit 0 to the vid dac. sda (vid1) - this is a dual function pin. when viden is low it acts as the i 2 c data/address line (sda) used to transfer voltage level and slew rate instructions to the isl6271. when viden is high this pin acts as bit 1 to the vid dac. vid2, vid3 - vid inputs to the error amplifier reference dac. used to control the core voltage when viden is high. gnd - device signal ground. connected to pgnd at a single point to avoid ground loops. pgnd - power ground return connection for the internal synchronous rectifier. forced pgood fault. converter operating in ccm at 420ma prior to applying a 320ma transient step. th is pushes the regulator beyond the overcurrent threshold of 700ma. the phase node three-stated and follows vout to 0v. 20s/div figure 14. forced pgood fault pgood delay = 186ns from disable. vout = 0.85v prior to en going low, 400ns/div figure 15. pgood delay typical operating performance (continued) test results from the intersil isl6271 customer reference board (crb). output filter on switcher made up of a 3.3h drumcore wi th 100m ? of dcr and an output capacitance of 4.7f. x5r; rcomp = 100k ? , vin = 3.7v unless otherwise noted. phase vout pgood pgood en phase vout isl6271
8 operational description initialization upon application of input power to the isl6271, the power good signal (pgood) will switch from low to high after four conditions are met - (1) vcc exceeds the power on reset ?rising threshold?, (2) the en pin is high and (3) the ldo input voltage (lvcc) is greater than 1.6v, (4) all three outputs are in regulation. figure 3 illustrates this start-up sequence. the outputs are powered on under a soft-start regime with the core output voltage defaulting to 1.3v (unless under vid control) and t he ldos at their fixed output levels. once the outputs are in regulation, the isl6271 will respond to a voltage change command via the i 2 c bus. core regulator output the isl6271 core regulator is a synchronous buck regulator that employs an intersil proprietary switch-mode topology known as synthetic ripple regulation (srr). the srr architecture is a derivative of the conventional hysteretic- mode regulator without the inher ent noise sensitivities and dependence on output capacitance esr. the topology achieves excellent transient response and high efficiency over the entire operating load rang e. output voltage ripple is typically under 5mv in continuous conduction mode (ccm) and under 10mv in dcm (diode emulation). the output core voltage is derived from the main battery pak (typically a single cell li-ion battery) and is programmable in 50mv steps between 0.85 and 1.6v. the output regulator set-point is controlled by an on-chip dac which receives its input either from the i 2 c bus or the vid input pins (vid0-vid3). table 1 identifies the vid co de states and corresponding output voltage. to minimize core voltage over-shoot and under-shoot between code states, the isl6271 implements programmable, voltage slew rate control via the i 2 c bus. the slew rate is a function of the data in the slew rate control register and also the soft-start capacitor; the slew rates in table 2 assume a soft-start capacitor value of 10nf. once the regulator has initialized, th e ic can be placed in a low quiescent state by pulling low the en pin. the regulator ?remembers? the last programmed voltage level and slew rate after each subsequent en cycle, and return to the previous set-point once en is brought high. table 1. voltage-set command bits i 2 c data byte or vid pins nominal output msb d3d2d1 lsb d0 xxxx 0000 0.850 xxxx 0001 0.900 xxxx 0010 0.950 xxxx 0011 1.000 xxxx 0100 1.050 xxxx 0101 1.100 xxxx 0110 1.150 xxxx 0111 1.200 xxxx 1000 1.250 xxxx 1001 1.300 xxxx 1010 1.350 xxxx 1011 1.400 xxxx 1100 1.450 xxxx 1101 1.500 xxxx 1110 1.550 xxxx 1111 1.600 vcc bflt# en vout pgood 1.3v 1.0v vpll, vsram system timing 2.8v typ. rising por threshold 2.6v typ. falling por threshold soft-start slew rate i 2 c programmable slew rate data transferred to the reference dac on the rising edge of scl during the ack bit i2c, scl figure 16. system timimg diagram isl6271
9 soft-start and slew rate control to assure stability and minimize overshoot at start-up and during dvm transitions, the isl6271 implements a controlled rise time of each regulator output. the slew rate control bits in table 2 are used to route one of 4 current sources to the soft pin. these current sources along with the soft-start capacitor will control the rate of rise of voltage during dvm transitions. the recommended 10nf soft-start capacitor will result in a typical slew rate of 1mv/s at start-up and the programmable dvm slew rates defined in table 2. slower or faster start-up and dvm transactions can be accommodated by selecting a smaller or lar ger soft-start capacitor. by default bits d5 and d4 are set to ?01? corresponding to a ss current of 10a. writing ?00? will result in a 5a of current whereas ?10? corresponds to 25a and ?11? corresponds to a typical source current of 4 7a. the expression i = cdv/dt can be used to solve for the appropriate slew rate. example: desired slew rate = 10mv/s fixed slew rate and the slew rate control bits are set to ?11?. then: isource = i 11 = 47na (nominal), therefore note: intel specifies a maximum slew rate for vcore transitions. to satisfy this requirement, the ss capacitor and soft pin sink/source current tolerances must be consid ered. refer to the electrical specification table and appropriate intel documents for details. note that when d5 and d4 are set to ?11? the maximum source current is 69na. under this condition, the slew rate would be 17.3mv/s if a 4.7nf ss capacitor varied by 15% negative. for this reason a 6.8nf capacitor is recommended when d5 and d4 are set to ?11?. undervoltage and overvoltage on vout if the output voltage of the switching regulator exceeds 112% of the soft pin voltage (programmed dac voltage) for longer than 1.5s, an overvoltage fault will be tripped and the phase node will be three-stat ed. hysteresis requires the voltage to fall to 106% before the fault is auto matically reset. an undervoltage occurs when the output voltage falls below 88% of soft pin voltage. once this fault is triggered, hysteresis sets the reset point to 90%. an undervoltage condition will occur if the outpu t dc current plus the ripple exceeds the current limit point for a period longer than the output capacitance hold-up time. loop compensation all three regulators are internally compensated for stability; however, an external resistor connected between the core regulator output and the fb pin can be used to alter the closed loop gain of the switching regulator and optimize transient response for a given output filter selection. the following combinations of component values are recommended: overcurrent limit to protect against an overcurrent condition, the core regulator employs a proprietary current sensing circuit that monitors the voltage drop across the internal upper mosfet. when an overcurrent condition is detected the controller will limit the output current and if the condition persists the output voltage level will drop below the undervoltage level tripping the pgood indicator. see ?applications section? for details. sram and pll ldos the two linear regulators on the isl6271 are designed to satisfy the power requirements of the sram and phase-lock loop circuitry internal to xscale processors. these regulators share a common input voltage pin (lvcc) that can be tied to the main battery pvcc or preferably to a lower system voltage to effect a higher conversion efficiency. it is recommended that lvcc be connected to a pre-regulated voltages between 1.8v - 2.5v. each ldo is internally compensated and designed to operate with a low-esr ceramic capacitors (x5r or better) between 2.2f and 3.3f. both ldos have overcurrent, undervoltage and thermal protection and share a common enable signal (en) with the core regulator, allowing them to be enabled/disabled together as required by the processor. bflt# the logic state of the bflt# output indicates whether the main battery input is adequate to power the system in normal operation. a battery low (or absent) condition is indicated by this pin being pulled low. upon initial application of battery power, it will indi cate a battery good condition when the battery voltage is gr eater than 2.8v (nominal), and it will sustain the battery good indication until the voltage drops below 2.6v (nominal). t he output is pulled actively low, with no main battery connected by tapping power from the secondary input, bbat. it is actively driven to bbat when the main battery is within the por thresholds. table 2. slew rate-set bit i 2 c data byte rate mv/s d5 d4 xx0 0xxxx 0.5 xx0 1xxxx 1 xx1 0xxxx 2.5 xx1 1xxxx 5 (eq. 1) c isource dv dt ------ --------------------- - = 47na 10mv u ---------------- ---------------- 4.7nf = = table 3. recommended key component values for core regulator lo cout rcomp 3.3h 4.7f 100k ? 4.7h 10f 50k ? isl6271
10 bbat the bbat pin is an input voltage to the isl6271 that supports the bflt# indicator function as described above. when the main battery is absen t, or of inadequate potential, the bbat input voltage supplies power to support the bflt# indicator. the input voltage must be between 2.25v and 3.75v for proper operation and is typically supplied from the system back-up battery. the maximum current drain from the bbat pin is 0.1a. pgood pgood is an open-drain output that indicates the status of the three regulators (vout, vsram, vpll). this output is held low until all outputs are within their specified voltage tolerance. as soon as outputs are in regula tion, the output is released and pulled high by an exter nal resistor tied to a compliant system voltage. this output can be and?d with other system power- good indicators that also have open-drain outputs. note that this is not a latched output and under a soft short condition on any of the regulators it is possible to see this pin oscillate at a frequency proportional to the fault current level and the fault monitoring hysteresis internal to the isl6271 regulator. phase node damping circuit to enhance system reliability and minimize radiated emission, the isl6271 implements an anti-ringing, phase node snubber while operating in diode emulation. the active snubber places a 50 ? (nominal) resistor across the output inductor when the low side synchronous rectifier is turned off to prevent reverse current. inter-ic communications communication between the host processor and the isl6271 takes place over a two-wire i 2 c interface. the bus consists of one bidirectional signal line, sda (data) and a clock pin input, scl generated by the bus master. both pins are pulled-high to a system voltage with external pull-up resistors. a typical pull-up resistor value for a single master/slave interface operating in normal mode is 5k ? . see the phillips specification listed in the reference section for specific details on the selection of the pull-up resistor. the bus supports both standard mode and fast mode data rates as defined by the phillips protocol. a typical i 2 c transmission is illustrated in figure 17. when the bus- resident master (processor) wants to communicate with a bus-resident slave (isl6271), it will pull the sda line low while the scl line is still high. this signals a ?start? condition. it will then clock the address of the desired slave device at a rate of one bit per clock cycle. the address is embedded in the first seven bits of the first byte transfer, with the eighth bit giving the directional information (read/write) for the next byte of information. when the slave detects an address match, it will hold the sda line low during the ninth clock pulse to acknowledge a match (ack). if the direction bit indicates a ?write? (send) byte, the slave will receive the byte clocked in by the master and will give an ?acknowledge? by again pulling the sda line low during the ninth clock cycle. the master then can either terminate transmission by issuing a ?stop? bit, or continue to transfer successive bytes until complete. multiple successive bytes ca n be transferred with only an acknowledge bit separating them until a ?stop? or repeated ?start? signal is given by the master. the data embedded in the byte is latched into its appropriate register(s) on the rising edge of the scl during the acknowledge pulse and is applied to the isl6271 dac. the internal dac on the isl6271 converts the 4 bit digital input as defined in table 1 into the reference voltage of the core regulator error amplifier. if the master issues a ?read? command to the isl6271, to verify the contents of the internal registers, the device will place the byte on the bus to be clocked in by the master. after the host master receives the byte, the cycle is terminated by a ?not acknowledge? signal, and a ?stop? bit. a ?stop? is generated by releasing the sda line to pull high during a high state on the scl line. p sr sr or p s or sr sda scl start or repeated start condition stop or repeated start condition 1 2789 msb acknowledgement signal from slave acknowledgement signal from receiver 9 12 3-8 ack ack clock line held low while interrupts are serviced byte complete, interrupt within slave figure 17. i 2 c data and clock isl6271
11 vid and slew rate program register in a typical xscale configuration, the processor?s ?power manager? will issue the voltage and slew rate commands to the isl6271 over it?s pwr_ i 2 c bus after the isl6271 acknowledges its address. the data byte is composed of two pieces of ?set? information: the prescribed voltage level embedded in bits d0-d3, and the prescribed transition slew rate (from the previous voltage to the target voltage) embedded in bits d4-d5. each set of bits is transmitted msb first. this protocol is depicted in figure 19. application guidelines every effort should be made to place the isl6271 as close as possible to the processor, with the orientation favoring the shortest voltage routing. the regulator input capacitors should be located close to their respective input pins. all output capacitors should be kept close to their respective output pins with the ground pi ns connected immediately to the ground plane. care should be taken to avoid routing sensitive, high impedance signals near the phase pin on the controller, and the attendant pcb traces . to minimize switching noise, it is important to keep the loop area associated with the phas e node and output filter as short as possible. it is also important that the input voltage decoupling capacitor c7 be located as close to the pvcc pin as possible and that it has a low impedance return path to the pgnd pin. in general a good approach to layout is to consider how switching current flows in a circuit, and to minimize the loop area associated with this current. in the case of the switching regulator, current flows from c7 through the internal upper p-mosfet, to the load through the output filter and back to the pgnd pin. to maximize the effectiveness of any decoupling capacitor, minimize the parasitic inductance between the capacitor and the circuit it is decoupling. notice that figure 19 illustrates the signal ground with red highlighting. all components associated with these terminals should be tied together first. be sure to make only one connection between this net and the pgnd pin to avoid ground loops and noise injection points into sensitive analog circuitry. figure 18. interface bit definition and protocol s 0001 10 00 0 s 0001 10 0 1 slave address command byte start p 0 d0 d1 d2 d3 d4 d5 x voltage slew x i 2 c send byte protocol i 2 c receive byte protcol data byte slave address start 0 a w a6 a5 a3 a2 a1 a0 a4 a6 a5 a4 a3 a2 a1 a0 w a d0 d6 d7 a stop a stop 1 p d1 d2 d3 d4 d5 set l1 4.7h part number rcomp, 50k c5 2.2f x5r c8 2.2f x5r en bflt# sda/vid1 scl/vid0 vsram vpll fb vout phase pvcc lvcc c4 6.8n x7r soft gnd c2 5k ? bbat vcc pgood bbat pgnd vid2 vid3 vcc viden single point connection between pgnd and gnd pins power ground. minimize the loop area associated with l1, c6 and the phase and pgnd pins. reg. en fault pwr_i2c vcc_sram vcc_pll vcc_core coin cell back-up c3 li-ion 4.2v to 2.60v r7, 10 ? c7 xscale p isl6271 1.8v or 2.5v c6 10f x5r { figure 19. typical application circuit 5k ? isl6271
12 loop stability calculations are simplified when using the isl6271 and are limited to the selection of a single feedback resistor, rcomp. the rcomp resi stor will affect the closed loop gain of the internal compensation network as in equation 1. empirical and theoret ical testing suggests that a value of 50k will provide the most ideal transient response to the expected xscale load and voltage transitions when used with the recommended 4.7h output inductor and 10f output capacitor. using the isl6271 evaluation board, a 50k feedback resistor resulted in a minimum of 60 degrees of phase margin under worst case line and load transitions. when placing the rcomp feedback resistor be sure to avoid routing it parallel to switching circuits especially the phase node, that could otherwise in duce noise into the fb pin. overcurrent protection and ripple current the ocl trip level inside the isl6271 is a function of the upper pmos output transistor?s on-resistance and overcurrent comparator threshold voltage. the device was designed to accommodate a maximum rms current of 470ma, and to accommodate this dc current level plus the associated ripple current, the oc limit of the isl6271 will not trip below 600ma. ripple current inside the isl6271 is defined by the expression, where ?fs? is the switching frequency of the converter. the architecture of the isl6271 is such that the switching frequency will increase with higher input voltage. this behavior attempts to keep the ripple current constant for a given output inductor, input voltage and output voltage. to minimize ripple current and preserve transient response, intersil recommends an output inductor between 3.3h and 4.7h. higher values of inductance will minimize the risk of tripling the overcurrent minimum threshold of 600ma. ssr theoretical operation the isl6271 is a pwm cont roller that uses a novel architecture developed by intersil called synthetic ripple regulation . the architecture operates similar to a hysteretic converter without the deficiencie s and noise sensitivities. reduced to its simplest form, the synthetic ripple regulator inside the isl6271 is made up of three elements as illustrated in figure 20: a transconductance amplifier (rippler amplifier), a window co mparator with hysteresis and an error amplifier. while operating in continuous conduction mode, the converter has a nat ural switching frequency of 1.2mhz delivering an ultra low output voltage ripple and exceptional transient response as illustrated in figures 23 and 24. figure 20 illustrates the two control loops inherent to the srr architecture. the inner loop consists of the ripple amplifier, the window comparator, gate drive circuitry and the power stage. the outer loop controls the inner loop and is made up a high bandwidth error amplifier with internal and external compensation. ccm operation - heavy current figure 21 illustrates the ssr in ccm. when the upper p-mosfet is turned on, the phase voltage equals the input voltage and the ripple transconductance amplifier outputs a current proportional to the diff erence of the input and output voltage. this current will ramp the voltage on the ripple capacitor cr in figure 21. as this voltage reaches the upper threshold of the hysteretic comparator, the comparator output will switch low. after a propagation delay, the upper p-mosfet is turned off and the lower n-mosfet is turned on, forcing synchronous rectification. at this point, the ripple amplifier now has inputs of 0v and vout and will sink current to discharge the ripple capacitor. when the voltage across the ripple capacitor reaches the lower threshold of the hysteresis window, the window comparator outputs a high signal. after a propagation delay, the upper p-mosfet turns on, repeating the previous switching cycle. gcomp rc cc ? s1 + ? () rcomp cc s ? ? -------------------------------------------- = (eq. 2) iripple vin vout ? () lfs ? --------------------------------- - vout vin ------------- ? = (eq. 3) lo + - error amp rcomp vref(dac) input voltage synthetic ripple regulation simplified diagram + - window comparator on vout vin gm off vout gm iout = { ), ( , rc cc ton + - toff cr sink/source control gm amp ripple capacitor - output voltage voltage figure 20. simplified srr diagram vout phase voltage vrp hysteresis window figure 21. synthetic ripple regulation in ccm isl6271
13 light load operation - dcm a light load is defined when the output inductor ripple current reaches zero before the next switching cycle. under this condition, the isl6271 synchronous rectifier will turn off emulating a diode to prevent negative inductor current. as explained below, the switching frequency and losses associated with turning on the synchronous rectifier will be reduced to enhance the low current efficiency. the top waveform in figure 22 shows the phase voltage in dcm. the middle waveforms include the error amplifier voltage, ripple capacitor voltage and the boundaries of the hysteresis comparator which track the ea output. the waveform at the bottom is representative of the inductor current. notice that in a switching cycle the inductor current rises as the upper p-mosfet turns on, falls when the lower n-mosfet turns on, and stays at zero after the current reaches zero as a result of diode emulation. to understand the isl6271 light load operation, look carefully at the waveforms in the middle of figure 22. notice that the voltage across the ripple capacitor, vrp, has a minimum clamp voltage (typically 0.4v), and that the error amplifier can go below this voltage (typically clamped to 0.2v). in dcm, the voltage across ripple capacitor will be discharged each cycle to the clamp voltage. while the lower hysteresis is below this voltage, the ripple capacitor will remain clamped keeping the up per p-mosfet off. as the ea voltage increases, so too, will the lower threshold of the hysteresis window until it reac hes the ripple capacitor clamp voltage (vclmp). at this point, the upper fet will be enabled and will turn on. the lighter the load, the lower the error amplifier output is, and the longer the ripple capacitor voltage stays at the vclmp voltage. this results in a phase node switching frequency that is proportional to load current (that is, lower switching losses and higher efficiency at lighter loads). in dcm the switching frequency will be lower than in a heavy load, ccm. a load transition from full load to no load will result in a finite period of time during which the error amplifier settles to a new steady state condition. as ill ustrated in figure 23, the ssr architecture inherent to the isl6271 responds within 6s of the mode change, slewin g the error amplifier output below the clamped ripple capacitor voltage and preventing the upper fet from turning on. prior to reaching the new stability point, the phase node applies four phase pulses before the controller forces the output voltage to the prescribed regulation point. once the output falls below the reference voltage the controller then pumps up the output voltage and enters its steady state dcm. mode changes that take the converter from ccm into dcm will have much higher output voltage spike than a load step that remains in ccm. compared with competitive solutions the isl6271 responds very well during this severe mode change and it is more than sufficient to meet vcore tolerance specifications as required by intel. note: note that the peak voltage in figure 23 is only 38mv, or less than one vid code transition above the reference set-point. transition between light load and heavy load unlike most control topologies that require two sets of circuits to control the light and heavy load operation, the srr control naturally switches between heavy and light load with the same control circuit. as the load gets lighter, the feedback forces the error amplifier output to a lower voltage and when the lower threshold of the hysteresis window is lower than vclmp, light load operation begins. the scope shot in figure 24 illustrates a mode transition from a dcm (10ma load current) to ccm (170ma) with trace 4 (grn) being the command pulse that initiates the mode change. prior to the load step, and while the converter is in dcm, the ripple voltage is approximately 10mv and the ripple frequency is 125khz. in ccm, the converter operates at a frequency of approximately 10x that of dcm and the ripple is reduced by more than a factor of two. figure 22. srr in dcm vea vrp vcmp vph lout clamped vrp> lower hys clamped vrp = > lower hys figure 23. ccm to dcm mode phase pulses before loop is closed dcm ccm loop closes 6s after mode change isl6271
14 measured core voltage conversion efficiency the actual efficiency of the isl6271 switching regulator is illustrated in figure 3 from 10ma to 500ma, and at two important input voltages. the first, 3.0v, is typical of a li-ion end of charge (eoc) battery voltage. the second, 3.6v, is typical of the ?plateau voltage? where most of the battery energy is available. once a li-ion battery reaches 3.0v, there is very little energy left in the battery and discharging it significantly below this point can compromise the number of charge cycles the battery will a ccept. recall that the 2.76v falling por threshold on the isl6271 acts to prevent a deep discharge condition from occurring. the efficiency curves in figure 3 were taken at room temperature using the isl6271 evaluation board. the output i nductor used is an ultralow profile, drumcore device with a dcr of 100m ? . thermal management although the isl6271 is char acteristically a low heat generator, it will generate some heat as a result of the inefficiencies in power conversion. the worst-case internal power dissipation should be less than 170mw translating into a 7c rise in junction tem perature above ambient. if the temperature of the chip does exceed 150 10c as a result of a high ambient temperature, the controller will disable the outputs until the temperat ure decreases by 45c. powering intel xscale processors intel identifies ten power domains required for powering xscale processors. of these ten power domains or voltages, many may be strapped together as in figure 25 and supplied by a single regulator. these voltages however must be applied systematically to th e processor and two pins, sys_en and pwr_en facilitate this power sequence. the pwr_en pin is dedicated to enabling the core, pll and sram power domains and should be connected to the isl6271 enable pin. the sys_en pin is responsible for enabling the system regulator. figure 27 illustrates one possible configuration using the intersil el7536 to power five of the 10 domains. note: intel warns that an improper power sequence can damage the processor. refer to the appropriate intel applications material to ensure proper voltage sequencing. design notes refer to table 3, "recommended key component values for core regulator". 1. do not leave pins vid2(5) or pin vid3(6) floating when using the i 2 c bus. tie these pins to gnd (16). 2. make sure that load current on vout returns to the pin (7) (pgnd). pin 16 (gnd) functions as a quiet return for the lvcc loads. it is internally tied to the device substrate (pin 21). tie pin 16 to pin 7 at a single point as in figure 19. 3. select the output capacitor for vsram and vpll as follows: 2.2f 15 internal esd structures the isl6271 input/output pi ns are protected from overvoltage conditions by clamping the pin to one diode drop above or below the vcc voltage rail. during shutdown it is possible that the sda and scl pins have a voltage greater than vcc. under this condition, the esd diodes will provide a reverse current path to circuitry on vcc that can act as a load on the back-up battery. to avoid this condition interrupt vcc from external circuitry if a voltage greater than vcc is expected on any of the pins identified below. layout recommendation since the isl6271 can operate at a high switching frequency, it is especially important to apply good layout practices. decoupling of the regulator?s input voltage (pvcc) and minimizing the loop area associated with the phase node output filter is essential for reliable operation. return currents from the load should find a low impedance path to the pgnd pin on the ic (pin 8). ideally, the core voltage would be distributed to the embedded processor on a low impedance power plane; however, a 30-50mil, short trace should be sufficient. when implementing dvm it is important to minimize inductance between the load and the output filter. the processors can command slew rates of up to 200ma/ns and local decoupling at the processor socket is essential to satisfying this requirement. references [1] isl6292 data sheet - battery charger [2] el7536 data sheet - system regulator [3] c-code examples for pwr_i2c bus communication - intersil support documentation available upon request. [4] phillips i 2 c bus specification [5] http://www.semiconducto rs.philips.com/buses/i2c/ [6] technical brief tb389 ? pcb land pattern design and surface mount guidelines for mlf packages? figure 26. internal esd structures gnd pvcc lvcc vout en scl sda vcc fb pgood bflt# vpll vsram soft gnd bbat pgnd gnd output cap vcc lpf pvcc input cap fb res output inductor 5x5x1mm soft-start cap ldo output caps single pt. gnd figure 27. component placement and top copper isl6271
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl6271 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l20.4x4 20 lead quad flat no-lead plastic package (compliant to jedec mo-220vggd-1 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.50 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n202 nd 5 3 ne 5 5 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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